The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which is capable of decreasing the capacitance between bit lines and storage nodes and a method for manufacturing the same.
In high integration applications of DRAM (dynamic random access memory) devices which have unit cells composed of a MOS (metal oxide semiconductor) transistor and a capacitor, it is an important to increase the capacitance as well as to decrease the area of capacitors. The capacitance of capacitors is proportional to the area of the capacitor and as a result capacitors often times end up occupying a disproportionate amount of area in a chip.
In order to form a capacitor having high capacitance within a narrow area, attempts to increase the height of the capacitor and to decrease the thickness of a dielectric layer have been made.
However, if the height of a capacitor is increased, a problem can arise in that the size of a step between a cell region and a peripheral region increases. If the thickness of a dielectric layer is decreased, a problem can arise in that leakage current increases as the thickness of the dielectric layer decreases.
In order to address these problems, recently, a method has been proposed, in which a buried type gate is used to decrease bit line parasitic capacitance by about a half so that the capacitance of a capacitor required for maintaining the sense amplifier drivability to the same level can be substantially decreased.
Nevertheless, as the continued march to decreasing in the area of a cell continuously proceeds, it is necessary to take steps that further decrease bit line parasitic capacitance.
The bit line parasitic capacitance is thought to be contributed from 1) the capacitance between a bit line and a word line, 2) the capacitance between the bit line and a storage node, 3) the capacitance between bit lines and 4) the capacitance between the bit line and a substrate.
Among these components, components 3) and 4) contribute an insignificant portion below 5% in the entire bit line parasitic capacitance. Each of components 1) and 2) contributes by about half of the bit line parasitic capacitance.
The buried type gate can decrease component 1) to about one tenth so that the entire bit line parasitic capacitance can be decreased to about half.
Under this situation, a remaining technical subject is to decrease the capacitance between the bit line and the storage node. If this is done, considering the fact that components 3) and 4) are insignificant, it is likely that the entire bit line parasitic capacitance can be significantly decreased.
In order to decrease the capacitance between the bit line and the storage node, the distance between the bit line and a storage node contact should be increased as much as possible.
Nonetheless, since the storage node contact cannot but be formed by using a self-aligned contact type with respect to the bit line due to the highly resolved compact pattern, the distance between the bit line and the storage node contact cannot but be is controlled by the width of a bit line spacer.
Therefore, in order to decrease the capacitance between the bit line and the storage node, the thickness of the bit line spacer should be increased. However, if the thickness of the bit line spacer is increased, undesirable side effects arise in that the contact area between the storage node contact and the substrate decreases and the drivability of a semiconductor device deteriorates. Thus, it is difficult to actually adopt the way of increasing the thickness of the bit line spacer.
Also, when forming the storage node contact in the self-aligned contact type by etching, the bit line spacer comprises a nitride layer so as to secure etching selectivity with respect to an interlayer dielectric comprising an oxide-based layer. In this regard, because the nitride layer has high dielectric constant compared to the oxide layer, the capacitance between the bit line and the storage node can increase.